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<\/a><\/p>\nHow does Make work?<\/h3>\n
The main goal of Makefile is to compile the files of your code that need to be compiled. It does this based on what files have changed. But when the files in the interpreted programming language change, nothing needs to be recompiled. You must keep in mind that when the program runs, the most recent version of the file is used.<\/p>\n
Here is a diagram showing the example dependency graph that you might build with Make. You must not that the file will get recompiled If any file’s dependencies change:<\/p>\n
Every MakeFile consists of a set of rules, and a rule looks like this:<\/p>\n Let us take a closer look at the fields in the syntax of writing a rule:<\/p>\n The targets are nothing but file names, separated by spaces. Mostly, there is only one per rule.<\/p>\n The prerequisite file is also file names, separated by spaces. However, you need to keep in mind that the files you specified need to exist before the commands for the target are run. Prerequisites are also called dependencies.<\/p>\n The commands are a set of actions or a series of steps typically used to make the target(s). You must always bear in mind that commands always start with a tab character and not spaces. If at all you give spaces instead of a tab, make will fail.<\/p>\n Before we jump into the action of Make, let us print the cliched \u201chello world\u201d statement to understand how to write make and execute them. First of all, you need to have \u201cMake\u201d installed in your system, if you don\u2019t you can simply use the command \u201csudo apt install make\u201d.<\/p>\n We need a file to write the set of instructions right, well, there are countless ways of creating it, you can use, nano, vim, vi, gedit, cat and so many more, the only thing that is important is that the name of the file must either be \u201cMakefile\u201d or \u201cmakefile\u201d. Once you create the file, write the following piece of code in it:<\/p>\n Once you have written it, save and close it. To execute it, simply type the command \u201cmake\u201d in the terminal, and you will get the following output:<\/p>\n Before we actually head-on and understand variables, conditionals, functions, and more, let us get our basics straight and understand how targets, prerequisites, and commands work by looking at some simple and small examples.<\/p>\n Let us create a Makefile that has 3 separate rules, when you run \u201cmake blah\u201d in the terminal, it will build a program called \u201cblah\u201d in the following series of steps:<\/p>\n 1. Since make is given \u201cblah\u201d as the target, it searched for this target<\/p>\n 2. \u201cblah\u201d requires \u201cblah.o\u201d, so it searched for \u201cblah.o\u201d<\/p>\n 3. \u201cblah.o\u201d requires \u201cblah.c\u201d. co it searches for this target.<\/p>\n 4. However, \u201cblah.c\u201d has o dependencies, so it runs the \u201cecho\u201d command<\/p>\n 5. Then the \u201ccc -c\u201d command is run as all of the \u201cblah.o\u201d dependencies are finished<\/p>\n 6. Then the \u201ccc\u201d command as all of the \u201cblah\u201d dependencies are finished<\/p>\n 7. And voila! \u201cBlah\u201d is now a fully compiled C program.<\/p>\n And here is the output, executed just like we anticipated!!<\/p>\n Let us look at a few more examples before proceeding further.<\/p>\n In the below-shown makefile, we only have a single target called \u201ca_file\u201d, so the default target is the first target, so the \u201ca_file\u201d will run.<\/p>\n And when we execute the Makefile, we will get the following output:<\/p>\n In the below-shown makefile, all we did is add a touch command to create \u201ca_file\u201d.<\/p>\n And we get the output as expected nothing special, we also created the file \u201ca_file\u201d, which we can see by running the \u201cls\u201d command<\/p>\n But the special part is when you run the program again, Make is clever enough to not create another \u201ca_file\u201d but tells you that it is already created and up to date!<\/p>\n If we now make this program slightly more complex by depending the target \u201ca_file\u201d on \u201cb_file\u201d, the target will first look at its list of dependencies, and if any of them are older, it will first run the targets for those dependencies, and then run itself. However, the second time you execute this program, neither target will run because both targets exist.<\/p>\n So in the command shown below, first the target \u201cb_file\u201d will run followed by \u201ca_file\u201d. Anagin you can check if the file \u201cb_file\u201d is successfully created or not by using the ls command.<\/p>\n Now that we got the hang of how Makefiles work, and how the program executes, let us dive deeper and explore things like targste, variables, conditional statements, functions and more.<\/p>\n If you want to make multiple target and run all of them, you can simply make an all target<\/p>\n <\/p>\n When there are multiple targets for a rule, the commands will be run for each target specified. We can use the \u201c$@\u201d which is an automatic variable that contains the target name. Here is an example:<\/p>\n <\/p>\n Infact, the above shown program is the same as the program shown below:<\/p>\n And we even get the same output:<\/p>\n In Make variables can only be strings, they can\u2019t be integer, float. Booleans, etc, just plain strings. You typically use, \u201c:=\u201d but \u201c=\u201d also works. Let us look at an example to get a better understanding:<\/p>\n Here is the output of the program shown in the above screenshot:<\/p>\n Reference variables on the other hand use \u201c${}\u201d or \u201c$()\u201d, here is an example<\/p>\n And the output for the above shown code:<\/p>\n <\/p>\n In make, there are 2 flavor variables:<\/p>\n Here is an examples using both the Recursive and simply expanded variables:<\/p>\n <\/p>\n And the output of the code shown above:<\/p>\n The simply expanded variable allows you to append a variable as shown:<\/p>\n Here we appended \u201chello\u201d (as a variable) to \u201cthere\u201d as seen below:<\/p>\n Another variable is \u201c?=\u201d, it only sets variables if they have not yet been set as shown in the below example:<\/p>\n If you think of giving spaces to your variables, you can do so, However, Spaces at the end of a line are not stripped, but those at the start are. Therefore, if you want to give spaces in a proper and professional way, create a variables called \u201c$(nullstring)\u201d<\/p>\n As you can see in every place we put the null string variables we get a blank space in the output as shown below:<\/p>\n If at all you are wondering what happens if we don\u2019t define a variable? The answer is that they will simply be an empty string.<\/p>\n As you can see even though we used the variables \u201cnowhere\u201d, we did not define it, but it still acts as an empty string.<\/p>\n You can actually override the variables that come from the command line by using override. Here is an example:<\/p>\n \u201cDefine\u201d is actually just a list of commands, don\u2019t confuse it with a function. Here is an example:<\/p>\n You can also assign variables for specific targets as shown below:<\/p>\n Variables can also be set for specific patterns as shown below:<\/p>\n There are many automatic variables that we can use in makefiles, but only a few showup.<\/p>\n In make files we can use either \u201c*\u201d or \u201c%\u201d as wildcards, but they mean entirely different things. Let’s look at the difference between th 2.<\/p>\n This wildcard searches your filesystem for matching filenames<\/p>\n This wildcard is used for the following tasks:<\/p>\n a. matches one or more characters in a string. This match is called the stem.<\/p>\n b. takes the stem that was matched and replaces that in a string.<\/p>\n c. used in rule definitions and in some specific functions.<\/p>\n In Make files we have the following fancy rules<\/p>\n 1. Implicit rules<\/p>\n 2. Static pattern rules<\/p>\n 3. Static pattern rules and filter<\/p>\n 4. Pattern rules<\/p>\n 5. Double-colon Rules<\/p>\n Let us look at each one in detail along with an example:<\/p>\n When make is compiling c programs, it uses a automatic rules, make calls these \u201cimplicit rules\u201d here is a list of the Implicit rules:<\/p>\n \u201cn.o\u201d is made automatically from \u201cn.c\u201d with a command of the form $(CC) -c $(CPPFLAGS) $(CFLAGS)<\/p>\n n.o is made automatically from n.cc or n.cpp with a command of the form $(CXX) -c $(CPPFLAGS) $(CXXFLAGS)<\/p>\n n is made automatically from n.o by running the command $(CC) $(LDFLAGS) n.o $(LOADLIBES) $(LDLIBS)<\/p>\n Here is an example to build a C program without explicitly telling Make how to do the compilation:<\/p>\n Static [pattern rules is another way to write less in a Makefile!the syntax we use is shown below:<\/p>\n The basic idea is that the given target is matched by the target-pattern (through a % wildcard). Here is an example:<\/p>\n The filter can be used in static pattern rules to match the correct files. In the example shown below, I made up the .raw and .result extensions.<\/p>\n Pattern rules are best used for<\/p>\n 1. Defining your own implicit rules<\/p>\n 2. Used as a simpler form of static pattern rule.<\/p>\n Double colon rules are very seldom used. These rules allow multiple rules to be defined for the same target. You must be careful while using them and not get confused with single colons, as a warning would be printed and only the second set of commands would run.<\/p>\n To stop a command from being printed, use the at the rate (@) symbol before the command. You can also run make with \u201c-s \u201cto add an at the rate symbol (@) before each line.<\/p>\n Each command runs in a new shell<\/p>\n Speaking of shell, every makefile\u2019s default shell is the \/bin\/sh however, you can change this by using the variable \u201cSHELL\u201d at the beginning of the program as shown below:<\/p>\n We handle different errors by using the following characters:<\/p>\n We can use \u201c-k\u201d when running make to continue running even if it faces errors.<\/p>\n We can use \u201c-\u201d before a command to suppress the error<\/p>\n We can use \u201c-i\u201d to make to have this happen for every command<\/p>\n You can simply interrupt or kill make in the middle of something by pressing the key combination \u201cctrl\u201d + \u201cc\u201d. It will also delete the newer targets it just made.<\/p>\n If you want to recursively call a makefile, use the special variable \u201c$(MAKE)\u201d instead of \u201cmake\u201d. Why? Because it will pass the make flag for you and won\u2019t affect itself by them. Here is an example:<\/p>\n Another way to recursively call a makefile is by using export. The export directive takes a variable and makes it accessible to the command present in make, or most commonly called sub make commands.<\/p>\n We all know how the if-else statement works, the logic behind it is the same, the only thing that changes between various programming languages is the syntax. Let us look at one example to get a better idea of if-else statements in Makefiles:<\/p>\n The above program checks if the string is \u201cDataFlair\u201d or not. Let us now use this conditional statement in a few examples.<\/p>\n In make there are the following function:<\/p>\n 1. First functions<\/p>\n 2. String substitution<\/p>\n 3. Foreach function<\/p>\n 4. If function<\/p>\n 5. Call function<\/p>\n 6. Shell function<\/p>\n Let us dive deeper and understand each one of them with the help of an example:<\/p>\n The primary purpose of functions is text processing, you can also make your own functions using the call built in function.<\/p>\n The string substitution function finds whitespace separated word in the text that match pattern and replaces them with the replacement you specified.<\/p>\n The foreach function converts one list of words to another. It looks something like this:<\/p>\n The if function checks if the first argument is non-empty or empty. If at all the first argument is not empty, it runs the second argument, otherwise the third.<\/p>\n As we glimpsed earlier, the inbuilt call function supports creating basic custom functions. It is you who defined the function just by creating a variable. You will have to use the parameters $(0), $(1), etc. The syntax you use to create your own function is:<\/p>\n The shell function calls the shell, but it replaces the newlines with spaces.<\/p>\n Before we call it a day, let us look at some bonus features of makefile.<\/p>\n The backslash (\\) gives us the ability to use multiple lines when the commands are too long. Here is an example:<\/p>\n We can add \u201c.PHONY\u201d to a target to prevent make from confusing the phony target with a file name. In the example shown below, if the file \u201cclean\u201d is created, make clean will still be run.<\/p>\n<\/a><\/p>\nSyntax of the makefile command in linux<\/h3>\n
<targets>: <prerequisite>\r\n<command>\r\n<command>\r\n<command><\/pre>\n
1. <targets><\/h4>\n
2. <prerequisite><\/h4>\n
3. <commands><\/h4>\n
Printing \u201cHello World\u201d<\/h3>\n
<\/a><\/p>\n<\/a><\/p>\nBeginner examples<\/h3>\n
<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\nTargets<\/h3>\n
<\/a><\/p>\n<\/a><\/p>\nMultiple targets<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\nVariables<\/h3>\n
<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\nFlavors and modification<\/h3>\n
\n
<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a> <\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\nCommand-line arguments and override<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nList of commands and \u201cdefine\u201d<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nTarget specific variables<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nPattern specific variables<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nAutomatic variables<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nWildcards<\/h3>\n
1. *<\/h4>\n
<\/a><\/p>\n2. %<\/h4>\n
Fancy rules<\/h3>\n
Implicit rules<\/h4>\n
Compiling a C program:<\/h4>\n
Compiling a C++ program<\/h4>\n
Linking a single object file<\/h4>\n
<\/a><\/p>\nStatic pattern rules<\/h4>\n
targets...: target-pattern: prereq-patterns ...\r\ncommands<\/pre>\n
<\/a><\/p>\nStatic pattern rules and filters<\/h4>\n
<\/a><\/p>\nPattern rules<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nDouble – colon rules<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nCommands and execution<\/h3>\n
Command echoing\/silencing<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nCommand execution<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nDefault shell<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nError handling<\/h4>\n
1. -k<\/h5>\n
2. –<\/h5>\n
3. -i<\/h5>\n
<\/a><\/p>\n<\/a><\/p>\nInterrupting or Killing make<\/h4>\n
Recursively using make<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nUsing export for recursively calling a makefile<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nIf-else statement in Makefiles<\/h3>\n
<\/a><\/p>\n<\/a><\/p>\nChecking if a variable is empty or not<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nFunctions in Makefiles<\/h3>\n
First functions<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nString substitution<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nForeach function<\/h4>\n
$(foreach var, <list>, <text>)<\/pre>\n
<\/a><\/p>\n<\/a><\/p>\nIf function<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nCall function<\/h4>\n
$(call <variable>, <parameter>, <parameter>)<\/pre>\n
<\/a><\/h4>\n<\/a><\/p>\nShell function<\/h4>\n
<\/a><\/p>\n<\/a><\/p>\nBonus makefile features<\/h3>\n
Multiline<\/h4>\n
<\/a><\/p>\n.phony<\/h4>\n